Electronic devices generally include at least one processor and a memory device. Typically, the memory device is used by the electronic device to store data and instructions for the processor. A variety of memory devices are available in the art, including such common examples as Read Only Memory (ROM), Read Access Memory (RAM) and flash memory. Additionally, each of these examples is available in several different versions to satisfy differing design considerations that may be important in particular applications.
Recently, flash memory devices have found growing commercial success in the electronic device market. This commercial success is due in part to the ability of flash memory devices to store electronic data over long periods of time without an electric power supply. In addition, flash memory devices can be erased and programmed by the end user after they are installed in an electronic device. This combined functionality is especially useful in electronic device applications, such as cellular telephones, personal digital assistants, and computer BIOS storage, and other applications where power supply is intermittent and programmability is desired.
Like other types of memory devices, flash memory devices typically include an array of individual memory transistors that are oriented in rows and columns. This array is sometimes referred to as the core, and the memory transistors are often referred to as cells, or core cells. As is common practice in the memory device art, the control gates of the memory cells in each row of the core are usually connected to a series of word lines, thus forming individual rows of cells that can be accessed by selecting the corresponding word line. Similarly, the drain regions of the cells in each column of the core are connected to a series of bit lines, thus forming individual columns of cells that can be accessed by selecting the corresponding bit lines. Finally, the source regions of all of the cells in the array are connected to a common source line. In some flash memory devices the array of transistors is further subdivided into sectors of separate transistor arrays to provide added flexibility for the programming and erasing operations.
The data stored in each memory cell represents a binary 1 or 0, as is well known in the art. To perform a program, read or erase operation on a particular cell in the array, various predetermined voltages are applied to the control gate, drain region and source region of the memory cell. Thus, by applying these predetermined voltages to a particular bit line column, a particular word line row and the common source line, an individual cell at the intersection of the bit line and word line can be selected for reading or programming.
In one common type of flash memory device, non-volatility of the memory cells is achieved by adding a floating gate between the control gate and the substrate region of the transistors. Typically, the cells of the flash memory device are programmed by applying a predetermined raised voltage to the control gate and the drain region of the cell and grounding the source region. As a result, the voltages on the control gate and the drain region cause the generation of hot electrons that are injected onto the floating gate, where they become trapped. This electron transfer mechanism is often referred to as Channel Hot Electron (CHE) injection. When the programming voltages are removed, the negative charge on the floating gate remains, thereby raising the threshold voltage of the cell. The threshold voltage is then used during reading operations to determine if the cell is in a charged state, i.e., programmed (0), or whether the cell is in an uncharged state, i.e., erased (1).
Cells are read by applying a lower predetermined voltage to the control gate and the drain region and grounding the source of the cell. The current in the bit line is then sensed with a sense amplifier. If the cell is programmed, the threshold voltage will be relatively high and the bitline current will be zero, or at least relatively low, thus registering a binary 0. On the other hand if the cell is erased, the threshold voltage will be relatively low and the bit line current will be relatively high, thus registering a binary 1.
In contrast to the programming procedure, flash memory devices are usually bulk-erased by simultaneously erasing all the cells in a memory sector. One procedure for erasing an entire memory sector involves applying predetermined voltages to the common source line and all the word lines of the sector while the drain regions of the cells are left to float. This causes electron tunneling from the floating gate to the source region through Fowler-Nordheim (F-N) tunneling, thereby removing the negative charge from the floating gate of each of the cells in the memory sector.
Typically, the memory device is provided with a number of address pins that allow the user to specify individual groups of memory cells for various operations. As is well-known in the art, the number of address pins usually provided for selecting the rows of cells is equal to log2 X, where X is the number of word lines in the memory device. Similarly, the number of address pins provided for selecting column groups of cells is equal to log2Y, where Y is the number of bytes or words in each row of cells (a byte being eight cells and a word being sixteen cells). When the memory device is performing internal embedded functions, the address bits for the row and column bits will generally be generated by a state machine within the memory device instead of being provided by the user through the address pins. The memory device also provides a number of data pins for inputting and outputting the data stored in the core cells. Commonly, the number of data pins is equal to the number of cells in the column groups that are selected by the column address bits, e.g., eight or sixteen.
In order to translate the row and column address bits into the specific word lines and bit lines that must be selected for an operation, an X-decoder and a Y-decoder are usually provided in the memory device. As is well-known in the art, the X-decoder receives the row address bits and connects the selected word line that corresponds to the address signal to the appropriate circuits. For example, in the case of a reading operation, the X-decoder will connect the selected word line to a voltage boosting circuit.
Likewise, the Y-decoder receives the column address bits and connects the selected bit lines that correspond to the address signal to the appropriate circuits. Thus, in reading operations, the Y-decoder will connect each of the selected bit lines to a sense amplifier.
Typically, memory devices are also provided with a number of reference cells. Reference cells are well known in the art and are commonly used in a variety of comparing functions which compare the reference cell to the status of the core cells. One example of a reference cell is an erase verify reference (xe2x80x9cERVrfxe2x80x9d) cell. The ERVrf cell is used during erasing operations to verify that each of the core cells have been successfully erased. Thus, the threshold voltage (xe2x80x9cVtxe2x80x9d) of the ERVrf cell is compared with each of the previously erased core cells to verify that the Vt of each core cell is less than the Vt of the ERVrf cell.
Similarly, a program verify reference (xe2x80x9cPGMVrfxe2x80x9d) cell is also commonly provided in the memory device. The PGMVrf cell is used during programming operations to verify that each of the core cells have been successfully programmed. In contrast to the erase verify operation, the programming verify operation compares the Vt of the PGMVrf cell with each of the previously programmed core cells to verify that the Vt of these cells is higher than that of the PGMVrf cell. Generally, the Vt of the PGMVrf cell is higher than the Vt of the ERVrf cell, with the difference between the Vt of the PGMVrf cell and the ERVrf cell representing a minimum change in Vt (xe2x80x9cxcex94Vtxe2x80x9d) between programmed and erased states. Typically, the xcex94Vt may be about 2 V.
Another reference cell that is normally provided is a read reference (xe2x80x9cRrfxe2x80x9d) cell. The Vt of the Rrf cell is usually somewhere between the Vt of the PGMVrf cell and the ERVrf cell. In one example, the Vt of the Rrf cell is about 0.5 V higher than that of the ERVrf cell. Accordingly, the Rrf cell is used in a comparing function with the core cells to determine whether each of the cells is in a programmed or erased state.
Typically, predetermined fixed values for the Vt of each of the reference cells is selected by the memory device designer prior to manufacturing the memory devices. In selecting these fixed Vt values, the memory device designer must take into account the amount of variation that occurs in the initial Vt of the core cells during manufacturing of the memory devices. The designer must also consider the amount of time that will be required to adjust the Vt of the core cells during set up of the memory device so that all the cells have a Vt below the predetermined fixed value of Vt for the ERVrf cell. In some memory devices, however, the time required to adjust the Vt of the core cells can be especially time consuming. Furthermore, some types of memory devices have a limited capacity to adjust the Vt of the core cells. In these cases the xcex94Vt may become unacceptably small and may affect the performance of the memory device after the expected manufacturing variations are factored in when predetermining the Vt value of the reference
A memory device setup procedure is provided for adapting reference cells to core cells. One advantage of this procedure is that the initial threshold voltages of the core cells do not need to be changed during setup of the memory device. In one stage of the method, an erase verify reference cell is adapted to the core cells until substantially all of the core cells have threshold voltages less than the threshold voltage of the erase verify reference cell. In another stage of the method, a program verify reference cell is setup by increasing the threshold voltage of the program verify reference cell by a desired change in voltage above the threshold voltage of the erase verify reference cell. A read reference cell is setup by changing the threshold voltage of the read reference cell so that it is intermediate between the erase verify reference cell and the program verify reference cell. Comparing circuits are also provided for changing the threshold voltages of the reference cells to the desired levels.